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SDRAM

SDRAM, abbreviated as Synchronous Dynamic Random Access Memory, is a DRAM semiconductor memory that can operate faster than conventional DRAM. It is popularly utilized as the random-access memory in a computer. SDRAM is synchronized with the clock speed for which the microprocessor is optimized. The speed of SDRAM is measured in MHz and not in nanoseconds (ns). This makes it less complicated to calculate the bus speed and the RAM chip speed. The RAM clock speed can be converted into nanoseconds by dividing the chip's speed by 1. For example, an 83 MHz RAM would be equal to 12 ns. 

SDRAM has been widely utilized in computers and related technology; after the introduction of SDRAM, several generations of double data rate RAM were developed like DDR, also known as DDR1. DDR2, DDR3, DDR4, and DDR5….

SDRAM became so popular after its introduction in 1996 that it has exceeded the use of DRAM in computers as the main form of dynamic RAM used across the computing spectrum, particularly for random access memory.

Advantages and Disadvantages

It is crucial to know about the advantages and disadvantages of any technology before you decide to use it in any electronic circuit design or project. SDRAM has been popular in the market for several computer memory applications and particularly for RAM. The advantages of SDRAM are as follows:

  • Simple design
  • Low cost
  • Speed
  • The complex manufacturing process required
  • DDR versions of SDRAM double the data rate of basic SDRAM by utilizing both edges of the clock cycle

Besides the advantages, SDRAM has its disadvantages in certain applications as well:

  • High consumption of power
  • This memory is volatile and loses its memory once the power is removed.
  • Data needs refreshing
  • It is slower than the SRAM.

Development of SDRAM

The initial ideas of SDRAM were introduced in the 1970s and have been in existence for many years. One of the first commercial SDRAM introduced was KM48SL2000 by Samsung in 1993. This did not immediately become popular. However, it was relatively quick to establish once the idea was established. As the speed of SDRAM was improved, in 2000, SDRAM had virtually replaced the standard DRAM technology in most computer applications. To ensure that SDRAM technology is interchangeable, the industry body for semiconductor standards, JEDEC, utilized its first SDRAM standard in 1993. This created an open standard for SDRAM. It also made it easier for the developers to use the product from more than one manufacturer and still have a second source option.

When the basic SDRAM was established, further developments took place. JEDEC established a type of SDRAM known as DDR or double date rat according to their developed standard 79C, which was updated later on into two more versions. After DDR SDRAM, another option known as DDR2 SDRAM was developed in 2003 when two clock rates were available. It was considered that the version of DDR2 SDRAM was inferior to the previous version of DDR SDRAM. However, as its speed increased, the performance exceeded that of DDR SDRAM. Later on, the next version, DDR3 SDRAM, was released. Its prototype was announced in 2005. However, it was 2007 when it initially started being used by the computer motherboard.

When choosing any memory, whether random access memory or any other functions, it is crucial to consider both advantages and disadvantages.


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Enrgtech #
Manufacturer Part No
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Rohs Verified
MT48LC16M16A2P-6A:G, Micron
633 In Stock
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1 +
£ 4.80
10 +
£ 4.21
90 +
£ 3.88
Alliance Memory
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AS4C16M16SA-7TCNTR, Alliance Memory
998 In Stock
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1000 +
£ 2.80
2000 +
£ 2.67
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MT48LC8M16A2P-6A :L, Micron
108 In Stock
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1 +
£ 6.00
10 +
£ 5.02
90 +
£ 4.15
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IS42S16800F-7TL, ISSI
214 In Stock
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108 +
£ 2.33
Rohs Verified
IS42S16400J-7TLI, ISSI
8422 In Stock
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108 +
£ 2.02
Alliance Memory
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AS4C128M16D2A-25BCN, Alliance Memory
207 In Stock
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209 +
£ 8.16
418 +
£ 7.76
627 +
£ 7.63
Alliance Memory
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AS4C32M16SB-7TIN, Alliance Memory
214 In Stock
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108 +
£ 12.06
324 +
£ 11.53
540 +
£ 11.15
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MT46V32M16P-5B :J, Micron
150 In Stock
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1 +
£ 5.86
10 +
£ 5.56
80 +
£ 5.29
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S27KS0643GABHV020, Infineon
334 In Stock
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4 +
£ 4.64
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W631GG8NB12I, Winbond
208 In Stock
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210 +
£ 4.09
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W9812G6KH-6I, Winbond
862 In Stock
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108 +
£ 1.92
Alliance Memory
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AS4C4M16SA-7BCN, Alliance Memory
1042 In Stock
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348 +
£ 2.10
696 +
£ 2.07
1044 +
£ 1.94
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IS42S32400F-7TL, ISSI
214 In Stock
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108 +
£ 3.06
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IS42S16160G-7TL, ISSI
538 In Stock
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108 +
£ 4.35
324 +
£ 4.23
540 +
£ 4.12
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W631GU6NB12I, Winbond
196 In Stock
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198 +
£ 3.11
594 +
£ 3.03
1188 +
£ 2.95
Alliance Memory
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AS4C16M16SA-6TIN, Alliance Memory
862 In Stock
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108 +
£ 3.76
324 +
£ 3.74
540 +
£ 3.60
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W631GU8NB12I, Winbond
196 In Stock
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198 +
£ 2.98
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W9864G6KH-6I, Winbond
646 In Stock
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108 +
£ 1.25
Cypress Semiconductor
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S27KS0643GABHV020, Cypress Semiconductor
334 In Stock
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4 +
£ 4.64
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MT46V16M16P-5B :M, Micron
2 In Stock
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£ 6.59
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£ 6.46
80 +
£ 6.25
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New Items
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MT48LC16M16A2P-6A:G, Micron

MT48LC16M16A2P-6A:G, Micron

Dynamic RAM, Micron Technology
New items
AS4C16M16SA-7TCNTR, Alliance Memory

AS4C16M16SA-7TCNTR, Alliance Memory

The Alliance Memory 256Mb SDRAM is a high-speed CMOS synchronous DRAM containing 256 Mbits. It is internally configured as 4 Banks of 4M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. Fast access time from clock: 5/5.4 ns Fast clock rate: 166/143 MHz Fully synchronous operation Internal pipelined architecture 4M word x 16-bit x 4-bank
New items
MT48LC8M16A2P-6A :L, Micron

MT48LC8M16A2P-6A :L, Micron

Dynamic RAM, Micron Technology
New items
IS42S16800F-7TL, ISSI

IS42S16800F-7TL, ISSI

Dynamic RAM, ISSI ISSI SDR SDRAM range offers synchronous interface with programmable CAS Latency (2/3 clocks). High speed data transfer is achieved using the pipeline process and the Synchronous DRAM SDR series offer burst read/write and burst read/single write making them ideally for use in computers applications. ISSI ’s SDR SDRAM devices come in a range of different organisations and memory sizes, operating on a 3.3V power supply. LVTTL interface Input/output signals refer to the rising edge of the clock input Programmable burst sequence: Sequential/Interleave; Programmable burst length Random column address every clock cycle Self-refresh and Auto Refresh mode
New items
IS42S16400J-7TLI, ISSI

IS42S16400J-7TLI, ISSI

Dynamic RAM, ISSI ISSI SDR SDRAM range offers synchronous interface with programmable CAS Latency (2/3 clocks). High speed data transfer is achieved using the pipeline process and the Synchronous DRAM SDR series offer burst read/write and burst read/single write making them ideally for use in computers applications. ISSI ’s SDR SDRAM devices come in a range of different organisations and memory sizes, operating on a 3.3V power supply. LVTTL interface Input/output signals refer to the rising edge of the clock input Programmable burst sequence: Sequential/Interleave; Programmable burst length Random column address every clock cycle Self-refresh and Auto Refresh mode
New items
AS4C128M16D2A-25BCN, Alliance Memory

AS4C128M16D2A-25BCN, Alliance Memory

The Alliance Memory 2Gb DDR2 is a high-speed CMOS Double-Data- Rate-Two (DDR2), synchronous dynamic random - access memory (SDRAM) containing 2048 Mbits in a 16- bit wide data I/Os. It is internally configured as a 8-bank DRAM, 8 banks x 16Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination(ODT). 8 internal banks for concurrent operation 4-bit prefetch architecture Internal pipeline architecture Precharge & active power down Programmable Mode & Extended Mode registers
New items
AS4C32M16SB-7TIN, Alliance Memory

AS4C32M16SB-7TIN, Alliance Memory

The Alliance Memory 512Mb SDRAM is a high-speed CMOS synchronous DRAM containing 512 Mbits. It is internally configured as 4 Banks of 8M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a Bank Activate command which is then followed by a Read or Write command. Auto Refresh and Self Refresh 8192 refresh cycles/64ms CKE power down mode Single +3.3V ±0.3V power supply
New items
MT46V32M16P-5B :J, Micron

MT46V32M16P-5B :J, Micron

Dynamic RAM, Micron Technology
New items
S27KS0643GABHV020, Infineon

S27KS0643GABHV020, Infineon

The Cypress Semiconductor S27KL0642/S27KS0642 is a 64 Mb HyperRAM which is a high-speed CMOS, self-refresh DRAM, with Hyper Bus interface. The array of the DRAM uses dynamic cells that require periodic refresh. The refresh control logic which is within the device, manages the refresh operations on the DRAM array when the memory is not being actively read or written by the Hyper Bus interface master (host). The DRAM array appears to the host as though the memory uses static cells that retain data without refresh, as the host is not required to manage any refresh operations. Hence, this memory is more accurately called or can be described as Pseudo Static RAM (PSRAM). Temperature Range: -40°C to +85°C Interface Bandwidth (MBps): 400MBps RoHS Compliant
New items
W631GG8NB12I, Winbond

W631GG8NB12I, Winbond

The Winbond SDRAM is a 1G bits DDR3 SDRAM which is organized as 8,388,608 words, 8 banks, 8 bits. This device achieves high speed transfer rates for various applications. Two data transfers per clock cycle Auto-precharge operation for read and write bursts Differential clock inputs
New items
AS4C4M16SA-7BCN, Alliance Memory

AS4C4M16SA-7BCN, Alliance Memory

The Alliance Memory 64Mb SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a Bank Activate command which is then followed by a Read or Write command. Fast access time from clock: 4.5/5.4/5.4 ns Fast clock rate: 200/166/143 MHz Fully synchronous operation Internal pipelined architecture 1M word x 16-bit x 4-bank
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